參數(shù)資料
型號(hào)： M50FW040NB5TG
廠商： 意法半導(dǎo)體
英文描述： 4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
中文描述： 4兆位（512 KB的× 8，均勻塊）3 - V電源供電的閃存固件樞紐
文件頁數(shù)： 14/53頁
文件大?。?/td> 278K
代理商： M50FW040NB5TG
Signal descriptions
M50FW040
14/53
2.1.10
Write Protect (WP)
The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being
changed. When Write Protect, WP, is set Low, V
IL
, Program and Erase operations in the
Main Blocks have no effect, regardless of the state of the Lock Register. When Write
Protect, WP, is set High, V
IH
, the protection of the Block determined by the Lock Register.
The state of Write Protect, WP, does not affect the protection of the Top Block (Block 7).
Write Protect, WP, must be set prior to a Program or Erase operation is initiated and must
not be changed until the operation completes or unpredictable results may occur. Care
should be taken to avoid unpredictable behavior by changing WP during Program or Erase
Suspend.
2.1.11
Reserved for future use (RFU)
These pins do not have assigned functions in this revision of the part. They must be left
disconnected.
2.2
Address/Address multiplexed (A/A Mux) signal descriptions
For the Address/Address Multiplexed (A/A Mux) Interface see <Blue>Figure 1., Logic
diagram (FWH interface), and <Blue>Table 1., Signal names (FWH interface).
2.2.1
Address inputs (A0-A10)
The Address Inputs are used to set the Row Address bits (A0-A10) and the Column
Address bits (A11-A18). They are latched during any bus operation by the Row/Column
Address Select input, RC.
2.2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs hold the data that is written to or read from the memory. They
output the data stored at the selected address during a Bus Read operation. During Bus
Write operations they represent the commands sent to the Command Interface of the
internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
2.2.3
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
2.2.4
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
2.2.5
Row/Column Address Select (RC)
The Row/Column Address Select input selects whether the Address Inputs should be
latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The
Row Address bits are latched on the falling edge of RC whereas the Column Address bits
are latched on the rising edge.
相關(guān)PDF資料
PDF描述
M50FW040NB5TP 4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
M50LPW116 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory
M50LPW116N 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory
M50LPW116N1T 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory
M50LPW116N5T 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FW040NB5TP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
M50FW080 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080K 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080K1 功能描述:閃存 3.6V 8M (1Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M50FW080K1G 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
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