參數(shù)資料
型號(hào): M50FW040NB5P
廠商: 意法半導(dǎo)體
英文描述: 4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory
中文描述: 4兆位(512 KB的× 8,均勻塊)3 - V電源供電的閃存固件樞紐
文件頁(yè)數(shù): 22/53頁(yè)
文件大?。?/td> 278K
代理商: M50FW040NB5P
Command interface
M50FW040
22/53
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations.
After power-up or a Reset operation the memory enters Read mode.
The commands are summarized in
Table 7: Commands
. Refer to
Table 7
in conjunction with
the text descriptions below.
4.1
Read Memory Array command
The Read Memory Array command returns the memory to its Read mode where it behaves
like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array
command and return the memory to Read mode. Once the command is issued the memory
remains in Read mode until another command is issued. From Read mode Bus Read
operations will access the memory array.
While the Program/Erase Controller is executing a Program or Erase operation the memory
will not accept the Read Memory Array command until the operation completes.
4.2
Read Status Register command
The Read Status Register command is used to read the Status Register. One Bus Write
cycle is required to issue the Read Status Register command. Once the command is issued
subsequent Bus Read operations read the Status Register until another command is issued.
See the section on the Status Register for details on the definitions of the Status Register
bits.
4.3
Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer Code and the
Device Code. One Bus Write cycle is required to issue the Read Electronic Signature
command. Once the command is issued subsequent Bus Read operations read the
Manufacturer Code or the Device Code until another command is issued.
After the Read Electronic Signature Command is issued the Manufacturer Code and Device
Code can be read using Bus Read operations using the addresses in
Table 6
.
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