參數(shù)資料
型號(hào): M50FLW080BN5P
廠商: 意法半導(dǎo)體
英文描述: 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
中文描述: 8兆位(13 × 64KB之座3 × 16 × 4KB的部門),3V電源固件集線器/低引腳數(shù)快閃記憶體
文件頁數(shù): 35/64頁
文件大?。?/td> 341K
代理商: M50FLW080BN5P
M50FLW080A, M50FLW080B
Firmware Hub/low-pin-count (FWH/LPC) interface Configuration
35/64
6
Firmware Hub/low-pin-count (FWH/LPC) interface
Configuration Registers
When the Firmware Hub Interface/Low Pin Count is selected, several additional registers
can be accessed. These registers control the protection status of the Blocks/Sectors, read
the General Purpose Input pins and identify the memory using the manufacturer code. See
Table 15
for the memory map of the Configuration Registers. The Configuration registers
are accessed directly without using any specific command code. A single Bus Write or Bus
Read Operation, with the appropriate address (including A22=0), is all that is needed.
6.1
Lock Registers
The Lock Registers control the protection status of the Blocks/Sectors. Each Block/Sector
has its own Lock Register. Three bits within each Lock Register control the protection of
each Block/Sector: the Write Lock Bit, the Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written. Care should be taken, though, when writing.
Once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be
made until it is cleared again by a reset or power-up.
See
Table 16
for details on the bit definitions of the Lock Registers.
6.1.1
Write Lock
The Write Lock Bit determines whether the contents of the Block/Sector can be modified
(using the Program or Erase Command). When the Write Lock Bit is set, ‘1’, the
Block/Sector is write protected – any operations that attempt to change the data in the
Block/Sector will fail, and the Status Register will report the error. When the Write Lock Bit is
reset, ‘0’, the Block/Sector is not write protected by the Lock Register, and may be modified,
unless it is write protected by some other means.
If the Top Block Lock signal, TBL, is Low, V
IL
, then the Top Block (Block 15) is write
protected, and cannot be modified. Similarly, if the Write Protect signal, WP, is Low, V
IL
, then
the Main Blocks (Blocks 0 to 14) are write protected, and cannot be modified. For details,
see
Appendix A
and
Table 16
.
After power-up, or reset, the Write Lock Bit is always set to ‘1’ (write-protected).
6.1.2
Read Lock
The Read Lock bit determines whether the contents of the Block/Sector can be read (in
Read mode). When the Read Lock Bit is set, ‘1’, the Block/Sector is read protected – any
operation that attempts to read the contents of the Block/Sector will read 00h instead. When
the Read Lock Bit is reset, ‘0’, read operations are allowed in the Block/Sector, and return
the value of the data that had been programmed in the Block/Sector.
After power-up, or reset, the Read Lock Bit is always reset to ‘0’ (not read-protected).
相關(guān)PDF資料
PDF描述
M50FLW080BN5TP 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080BNB5P 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080BNB5TP 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080AK5P 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
M50FLW080AK5TP 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
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