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| 型號： | M5-320/160-6YC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 6.5 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 34/42頁 |
| 文件大?。?/td> | 938K |
| 代理商： | M5-320/160-6YC |
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4MACH 5 Family
allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system
programmable through an IEEE 1149.1 Test Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the
block interconnect is called a segment. The second level of interconnect, the segment
interconnect, ties all of the segments together. The only logic difference between any two MACH
5 devices is the number of segments. Therefore, once a designer is familiar with one device,
consistent performance can be expected across the entire family. All devices have four clock pins
available which can also be used as logic inputs.
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block
resembles an independent PAL device, it has superior control and logic generation capabilities.
◆
I/O cells
◆
Product-term array and Logic Allocator
◆
Macrocells
◆
Register control generator
◆
Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local
feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect
line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment
interconnects provide connections between any two signals in a device. The
block feeder assigns
block interconnect lines and local feedback lines to the PAL block inputs.
Block
Interconnect
4
CLK
Block:
16 MCs
Segment:
4 Blocks
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
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