參數(shù)資料
型號(hào): M4A5-96/48-7VI
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 2/62頁(yè)
文件大?。?/td> 0K
描述: IC CPLD ISP 4A 96MC 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispMACH® 4A
可編程類(lèi)型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
宏單元數(shù): 96
輸入/輸出數(shù): 48
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤(pán)
10
ispMACH 4A Family
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
SWAP
D/T/L
Q
AP
AR
Power-Up
Reset
PAL-Block
Initialization
Product Terms
From Logic Allocator
Block CLK0
Block CLK1
Block CLK2
Block CLK3
To Output and Input
Switch Matrices
Common PAL-block resource
Individual macrocell resources
From
PAL-Clock
Generator
D/T/L
Q
AP
AR
Power-Up
Reset
Individual
Initialization
Product Term
From Logic
Allocator
Block CLK0
Block CLK1
To Output and Input
Switch Matrices
Individual Clock
Product Term
From PAL-Block
Clock Generator
SWAP
17466G-010
Figure 5. Macrocell
17466G-009
a. Synchronous mode
b. Asynchronous mode
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