參數(shù)資料
型號(hào): M4A5-96/48-7VI
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 1/62頁
文件大?。?/td> 0K
描述: IC CPLD ISP 4A 96MC 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispMACH® 4A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
宏單元數(shù): 96
輸入/輸出數(shù): 48
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
Publication# ISPM4A
Rev: M
Amendment/0
Issue Date: September 2006
Lead-
Free
Package
Options
Available!
ispMACH 4A CPLD Family
High Performance E2CMOS
In-System Programmable Logic
FEATURES
High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and ret feature
— SpeedLockingTM performance for guaranteed xed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Lead-free package options
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