參數(shù)資料
型號(hào)： M4A5-96/48-10VNI
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 28/62頁(yè)
文件大小： 0K
描述： IC CPLD 96MACRO 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： ispMACH® 4A
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
宏單元數(shù)： 64
輸入/輸出數(shù)： 48
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
34
ispMACH 4A Family
BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192
Central
Switch
Matrix
Block B
CLK0–CLK3
Block A
Block GX
Block HX
Block C
Block F
Block D
Block E
Block FX
Block CX
Block EX
Block DX
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
4
OE
8
16
8
4
16
24
8
16
36
4
8
24
36
4
8
16
4
16
OE
8
24
36
4
8
16
4
16
OE
4
8
36
24
16
8
16
8
4
16
OE
4
36
24
16
8
16
4
8
OE
4
36
24
16
8
16
4
8
4
8
36
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
36
4
OE
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
I/O Cells
Macrocells
72 X 90
AND Logic Array
and Logic Allocator
Clock
Generator
Input
Switch
Matrix
Output Switch
Matrix
OE
8
16
8
4
16
24
8
16
36
4
8
24
36
4
8
16
4
16
OE
8
24
36
4
8
16
4
16
OE
4
8
36
24
16
8
16
8
4
16
OE
4
36
24
16
8
16
4
8
OE
4
36
24
16
8
16
4
8
4
8
36
24
16
8
16
8
4
16
OE
8
16
8
4
16
24
8
16
36
4
OE
Block G
Block J
Block H
Block I
Block BX
Block O
Block AX
Block P
Detail A
Repeat Detail A
Block L
Block K
Block M
Block N
17466G-067
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