參數(shù)資料
型號: M48T59V-70MH6
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.330 INCH, PLASTIC, SOH-28
文件頁數(shù): 28/29頁
文件大?。?/td> 440K
代理商: M48T59V-70MH6
M48T59, M48T59Y, M48T59V*
8/29
WRITE Mode
The M48T59/Y/V is in the WRITE Mode whenever
W and E are low. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid
tDVWH prior to the end of WRITE and remain valid
for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs tWLQZ af-
ter W falls.
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms
AI01386
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A12
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI01387B
tAVAV
tEHAX
tDVEH
A0-A12
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT
相關(guān)PDF資料
PDF描述
M48T59V-70MH6E REAL TIME CLOCK, PDSO28
M48T59V-70MH6TR 0 TIMER(S), REAL TIME CLOCK, PDSO28
M48T59Y-70MH6F REAL TIME CLOCK, PDSO28
M48T86MH1E 1 TIMER(S), REAL TIME CLOCK, PDSO28
M4T32-BR12SH1 1 TIMER(S), REAL TIME CLOCK, DSS4
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M48T59V-70MH6TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM
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M48T59V-70PC1E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM
M48T59V-70PC1F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM
M48T59V-70PC1TR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM