參數(shù)資料
型號(hào): M48T129Y-85PM1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA32
封裝: PLASTIC, MODULE, DIP-32
文件頁(yè)數(shù): 4/30頁(yè)
文件大小: 483K
代理商: M48T129Y-85PM1
M48T129Y, M48T129V
12/30
Data Retention Mode
With valid VCC applied, the M48T129Y/V operates
as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
VCC falls between VPFD (max), VPFD (min) win-
dow. All outputs become high impedance and all
inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T129Y/V may re-
spond to transient noise spikes on VCC that cross
into the deselect window during the time the de-
vice is sampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T129Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
tREC after VCC reaches VPFD (max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
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