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參數(shù)資料
| 型號： | M48T129Y-85PM1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, DMA32 |
| 封裝： | PLASTIC, MODULE, DIP-32 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 483K |
| 代理商： | M48T129Y-85PM1 |
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M48T129Y, M48T129V
CLOCK OPERATIONS
TIMEKEEPER Registers
The M48T129Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
Reading the Clock
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (1FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af-
ter the READ Bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 14).
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (1FFFFh-1FFF9h,
1FFF1h) to the actual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 1FFF9h. Setting it to
a '1' stops the oscillator. When reset to a '0', the
M48T129Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T129YPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T129YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T18 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 64Kbit (8 Kb x 8) TIMEKEEPER㈢ SRAM |
| M48T18-100MH1 | 功能描述:RAM其它 8KX8 TIMEKEEP 100NS RoHS:否 制造商:Freescale Semiconductor 封裝:Tray |
| M48T18-100MH1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x 8 TIMEKEEPER SRAM |
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