參數(shù)資料
型號: M48T129V-70PM1
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP32
封裝: 0.600 INCH, PLASTIC, MODULE, DIP-32
文件頁數(shù): 29/30頁
文件大?。?/td> 483K
代理商: M48T129V-70PM1
M48T129Y, M48T129V
8/30
READ Mode
The M48T129Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
Figure 7. Address Controlled, READ Mode AC Waveforms
AI01197
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
AI02324
tAVAV
tAVQV
tAXQX
DATA VALID
A0-A16
DQ0-DQ7
VALID
DATA VALID
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相關代理商/技術參數(shù)
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