參數(shù)資料
型號(hào): M48T02-150PC1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
文件頁數(shù): 25/25頁
文件大?。?/td> 199K
代理商: M48T02-150PC1
M48T02, M48T12
Operation modes
2.2
Write mode
The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior
to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the
end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 5.
Write enable controlled, write AC waveform
Figure 6.
Chip enable controlled, write AC waveforms
AI01331
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A10
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI01332B
tAVAV
tEHAX
tDVEH
A0-A10
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT
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