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參數(shù)資料
| 型號： | M470T2953CZ3-CE7 |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.4 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | M470T2953CZ3-CE7 |
Rev. 1.6 March 2007
SODIMM
DDR2 SDRAM
Page 15 of 20
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0
°C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
75
105
127.5
195
327.5
ns
Average periodic refresh interval
tREFI
0
°C ≤ TCASE ≤ 85°C
7.8
s
85
°C < TCASE ≤ 95°C
3.9
s
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR2-800(E7)
DDR2-800(F7)
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
Units
Bin(CL - tRCD - tRP)
5 - 5 - 5
6 - 6 - 6
5 - 5 - 5
4 - 4 - 4
3 - 3 - 3
Parameter
min
max
min
max
min
max
min
max
min
max
tCK, CL=3
5
8
-
5
8
5
8
5
8
ns
tCK, CL=4
3.75
8
3.75
8
3.75
8
3.75
8
5
8
ns
tCK, CL=5
2.5
8
3
8
3
8
3.75
8
-
ns
tCK, CL=6
-
2.5
8
-
ns
tRCD
12.5
-
15
-
15
-
15
-
15
-
ns
tRP
12.5
-
15
-
15
-
15
-
15
-
ns
tRC
57.5
-
60
-
54
-
55
-
55
-
ns
tRAS
45
70000
45
70000
39
70000
40
70000
40
70000
ns
(VDD=1.8V, VDDQ=1.8V, TA=25oC)
* DM is internally loaded to match DQ and DQS identically.
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Non-ECC
M470T6554CZ3
M470T6554CZ0
M470T3354CZ3
M470T3354CZ0
M470T2953CZ3
M470T2953CZ0
Input capacitance, CK and CK
CCK
-
32
-
24
-
48
pF
Input capacitance, CKE , CS, Addr, RAS, CAS, WE
CI
-
34
-
34
-
42
Input/output capacitance, DQ, DM, DQS, DQS
CIO(400/533)
-
10
-
6
-
10
CIO(667/800)
-
9
-
5.5
-
9
12.0 Input/Output Capacitance
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