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參數(shù)資料
| 型號： | M44C092-V |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 62/80頁 |
| 文件大?。?/td> | 609K |
| 代理商： | M44C092-V |
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M44C092–V
M44C092–V
Rev. A2, 08-Nov-01
65 (80)
Combination mode 7: Pulse width modulation (PWM)
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 3 mode 9:
Pulse width modulation with the shift register data (SO)
The two compare registers are used to generarte two varied time intervals. The SSI data output selects which compare
register is used for the output pulse generation. In this mode both compare and compare mode registers must be pro-
grammed to generate the two pulse width. It is also useful to enable the single action mode for extreme duty cycles.
Timer 2 is used as baudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with the toggle
signal of Timer 2. The counter is driven by an internal or external clock source.
0000 00000
000 0
Counter 3
CM31
CM32
T3O
13816
000001 2345 6789 1011121314150 12345
TOG2
67 8
1
91112
10
14
13
0
2 3
14
15
0
01
SIR
SO
SCO
T3R
Figure 76. Pulse-width modulation
Combination mode 8: Manchester demodulation / pulse width demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3
Timer 3 mode 10:
Manchester demodulation / pulse width demodulation with Timer 3
For Manchester demodulation the edge detection stage must be programmed to detect each edge at the input. These
edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. A compare
register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit into shift
register. After that the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can be used to detect a time error and handle it with an interrupt routine.
Before activating the demodulator mode the timer and the demodulator stage must be synchronized with the bitstream.
The Manchester code timing consists of parts with the half bitlength and the complete bitlength. A synchronization
routine must start the demodulator after an interval with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by Timer 2 in this mode. The
Manchester decoder can also be used for pulse-width demodulation. The input must programmed to detect the positive
edge. The demodulator and timer must be synchronized with the leading edge of the pulse. After that a counter match
with the compare register 1 shifts the state at the input T3I into the shift register. The next positive edge at the input
restarts the timer.
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