參數(shù)資料
型號： M44C092-H
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 17/84頁
文件大?。?/td> 648K
代理商： M44C092-H
M44C892–H
M44C092–H
Rev. A2, 14-Dec-01
24 (84)
3.2.3
Bidirectional Port 5
This, and all other bidirectional ports include a bitwise
programmable Control Register (P5CR), which allows
the individual programming of each port bit as input or
output. It also opens up the possibility of reading the pin
condition when in output mode. This is a useful feature
for self testing and for serial bus applications.
The port pins can also be used as external interrupt inputs
(see figures 24 & 25). The interrupts (INT1 and INT6) can
be masked or independently configured to trigger on ei-
ther edge. The interrupt configuration and port direction
is controlled by the Port 5 Control Register (P5CR). An
additional low resistance pull–up/–down transistor mask
option provides an internal bus pull–up for serial bus ap-
plications.
The Port 5 Data Register (P5DAT) is I/O mapped to the
primary address register of address ’5’h and the Port 5
Control Register (P5CR) to the corresponding auxiliary
register. The P5CR is a byte-wide register and is config-
ured by writing first the low nibble then the high nibble
(see section 2.1 ”Addressing peripherals”).
Master reset
Q
V
DD
BP5y
Mask options
*
P5DATy
I/O Bus
D
IN enable
I/O Bus
*
Switched
V
DD
*
Static
Pull-up
(Data out)
*
S
*
V
DD
Static
Pull-down
pull-up
pull-down
Figure 24. Bidirectional Port 5
Bidir. Port
Data in
IN_Enable
BP53
P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
Decoder
Bidir. Port
Data in
IN_Enable
BP52
I/O–bus
Bidir. Port
Data in
IN_Enable
BP51
I/O–bus
Bidir. Port
Data in
IN_Enable
BP50
INT1
INT6
P5CR:
13764
Figure 25. Port 5 external interrupts
相關(guān)PDF資料
PDF描述
M44C892-H 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
M44C092-V 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
M48T02-120PC1 0 TIMER(S), REAL TIME CLOCK, PDIP24
M48T08Y-15MH1E REAL TIME CLOCK, PDSO28
M48T08Y-15MH1 0 TIMER(S), REAL TIME CLOCK, PDSO28
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