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參數(shù)資料
| 型號(hào)： | M43C505-XXX-Q44 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLCC-44 |
| 文件頁數(shù)： | 221/242頁 |
| 文件大?。?/td> | 3080K |
| 代理商： | M43C505-XXX-Q44 |
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8
2588F–AVR–06/2013
ATtiny261/461/861
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
directly addressing the whole address space. Most AVR instructions have a single 16-bit word
format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices
only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
4.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
4.3
Status Register
The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M44C090-XXX-FL16 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDSO16 |
| M44C090-XXX-DIT | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, UUC |
| M48ST59W-70MH1TR | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| M48ST59W-100MH1 | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| M48T02-150PC1 | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M43G | 功能描述:滑動(dòng)開關(guān) Std Sz Slide Switch RoHS:否 制造商:C&K Components 觸點(diǎn)形式:SPDT 開關(guān)功能:Momentary 觸點(diǎn)額定值: 端接類型: 執(zhí)行器:Extended, Side 安裝風(fēng)格:SMD/SMT 觸點(diǎn)電鍍:Silver 封裝: |
| M43P100KB30T601 | 功能描述:微調(diào)電阻 - 通孔 43 P 10U 10% T601 BO100 e3 RoHS:否 制造商:Vishay/Sfernice 產(chǎn)品:Trimmer Resistors - Multi Turn 產(chǎn)品類型:Multiturn 轉(zhuǎn)數(shù):14 錐度:Linear 電阻:10 kOhms 電壓額定值:250 V 端接類型:Pin 功率額定值:250 mW (1/4 W) 容差:10 % 溫度系數(shù):100 PPM / C |
| M43P100KB40 | 功能描述:微調(diào)電阻 - 通孔 3/4"REC 10ohms 10% RoHS:否 制造商:Vishay/Sfernice 產(chǎn)品:Trimmer Resistors - Multi Turn 產(chǎn)品類型:Multiturn 轉(zhuǎn)數(shù):14 錐度:Linear 電阻:10 kOhms 電壓額定值:250 V 端接類型:Pin 功率額定值:250 mW (1/4 W) 容差:10 % 溫度系數(shù):100 PPM / C |
| M43P101KB30T601 | 制造商:Vishay Dale 功能描述:43 P 100U 10% T601 BO100 E3 - Boxed Product (Development Kits) 制造商:Vishay Spectrol 功能描述:TRIMMER 20 TURN 100R 制造商:Vishay Spectrol 功能描述:TRIMMER, 20 TURN 100R 制造商:Vishay Spectrol 功能描述:TRIMMER, 20 TURN 100R; Track Resistance:100ohm; No. of Turns:18; Resistance Tolerance: 10%; Temperature Coefficient: 100ppm/C; Power Rating:500mW; Potentiometer Mounting:Through Hole; SVHC:No SVHC (18-Jun-2012); Adjustment ;RoHS Compliant: Yes |
| M43P101KB40 | 功能描述:微調(diào)電阻 - 通孔 3/4"REC 100ohms 10% RoHS:否 制造商:Vishay/Sfernice 產(chǎn)品:Trimmer Resistors - Multi Turn 產(chǎn)品類型:Multiturn 轉(zhuǎn)數(shù):14 錐度:Linear 電阻:10 kOhms 電壓額定值:250 V 端接類型:Pin 功率額定值:250 mW (1/4 W) 容差:10 % 溫度系數(shù):100 PPM / C |
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