參數(shù)資料
型號(hào): M41T56BN6
廠商: STMICROELECTRONICS
元件分類(lèi): 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP8
封裝: PLASTIC, DIP-8
文件頁(yè)數(shù): 5/24頁(yè)
文件大?。?/td> 163K
代理商: M41T56BN6
13/24
M41T56
Data Retention Mode
With valid VCC applied, the M41T56 can be ac-
cessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41T56 will automatically deselect, write protect-
ing itself when VCC falls between VPFD (max) and
VPFD (min). This is accomplished by internally in-
hibiting access to the clock registers and SRAM.
When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the battery and the clock reg-
isters and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protec-
tion continues for tREC.
For a further more detailed review of battery life-
time calculations, please see Application Note
AN1012.
Figure 16. Power Down/Up Mode AC Waveforms
Table 8. Power Down/Up Mode AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Table 9. Power Down/Up Trip Points DC Characteristics
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
Symbol
Parameter(1)
Min
Max
Unit
tPD
SCL and SDA at VIH before Power Down
0ns
tFB
VPFD (min) to VSS VCC Fall Time
300
s
tRB
VSS to VPFD (min) VCC Rise Time
100
s
tREC
SCL and SDA at VIH after Power Up
10
s
Symbol
Parameter(1,2)
Min
Typ
Max
Unit
VPFD
Power-fail Deselect Voltage
1.2 VBAT
1.25 VBAT
1.285 VBAT
V
VSO
Battery Back-up Switchover Voltage
VBAT
V
AI00595
VCC
tFB
tREC
tPD
tRB
VPFD
VSO
DATA RETENTION TIME
SDA
SCL
IBAT
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