參數(shù)資料
型號: M41T50Q6F
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, QCC16
封裝: 3 X 3 MM, LEAD FREE, QFN-16
文件頁數(shù): 3/23頁
文件大小: 288K
代理商: M41T50Q6F
11/23
M41T50
CLOCK OPERATION
The
eight
byte
clock
register
(see
2., page 12) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Reserved0, Seconds, Min-
utes, and Hours are contained within the first four
registers.
Bits D0 through D2 of Register 04h contain the
Day (day of week). Registers 05h, 06h, and 07h
contain the Date (day of month), Month, and
Years. Bit D7 of Register 01h contains the STOP
Bit (ST). Setting this bit to a '1' will cause the oscil-
lator to stop. When reset to a '0' the oscillator re-
starts within one second (typical).
Bits D6 and D7 of Clock Register 06h (Century/
Month Register) contain the CENTURY Bit 0
(CB0) and CENTURY Bit 1 (CB1).
Bit D6 of Register 0Ch (Alarm Hour Register) con-
tains the SQW Open Drain Bit (SQWOD). When
this bit is set to '1,' the Square Wave output will be-
come an open drain output and require a pull-up
resistor.
Note: A WRITE to ANY location within the first
eight bytes of the clock register (00h-07h), includ-
ing the 60Hz Bit and CB0-CB1 Bits will result in an
update of the system clock and a reset of the divid-
er chain. This could result in an inadvertent
change of the current time. These non-clock relat-
ed bits should be written prior to setting the clock,
and remain unchanged until such time as a new
clock time is also written.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
Digital Clock Input
The M41T50 requires an external square wave
clock source of 50Hz or 60Hz (45% to 55% duty
cycle) for the clock function. Bit D7 (60Hz bit) of
Register 05h (Date Register) is used to select be-
tween a 50Hz (60Hz Bit = '0') or a 60Hz (60Hz Bit
= '1') clock input frequency signal. The 60Hz Bit
defaults to '1' on power-up.
TIMEKEEPER Registers
The M41T50 offers 16 internal registers which
contain Clock, Alarm, and Flag Registers. The
Clock registers are memory locations which con-
tain external (user accessible) and internal copies
of the data (usually referred to as BiPORT TIME-
KEEPER cells). The external copies are indepen-
dent of internal functions except that they are
updated periodically by the simultaneous transfer
of the incremented internal copy. The internal di-
vider (or clock) chain will be reset upon the com-
pletion of a WRITE to any clock address (00h to
07h).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock address.
TIMEKEEPER and Alarm Registers store data in
BCD format.
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