參數(shù)資料
型號(hào)： M41T00M6F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOIC-8
文件頁(yè)數(shù)： 24/25頁(yè)
文件大?。?/td> 202K
代理商： M41T00M6F
Device operation
M41T00
2.4
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.5
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.6
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
相關(guān)PDF資料
PDF描述
M41T00M6E REAL TIME CLOCK, PDSO8
M41T00M6 0 TIMER(S), REAL TIME CLOCK, PDSO8
M41T0DS6 REAL TIME CLOCK, PDSO8
M41T0DS6T REAL TIME CLOCK, PDSO8
M41T0M6T 0 TIMER(S), REAL TIME CLOCK, PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M41T00M6F-CUT TAPE 制造商:ST 功能描述:M41T00 Series 2 - 5.5 V 32 kHz Serial I2C Real Time Clock - SOIC-8
M41T00S 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock
M41T00S_08 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial access real-time clock
M41T00SC64 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Real-Time Clock + 64Kbit (8192 x 8) EEPROM
M41T00SC64MY6E 功能描述:電可擦除可編程只讀存儲(chǔ)器 SERIAL REAL TIME CLOCK 64Kb 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
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