參數(shù)資料
型號: M41T00CAPPC1
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: REAL TIME CLOCK, PDIP24
封裝: ROHS COMPLIANT, PLASTIC, DIP-24
文件頁數(shù): 5/27頁
文件大?。?/td> 224K
代理商: M41T00CAPPC1
M41T00CAP
Operation
3.8
WRITE mode
In this mode the master transmitter transmits to the M41T00CAP slave receiver. Bus
protocol is shown in Figure 9. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The device slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and after each data byte.
Figure 9.
WRITE mode sequence
3.9
Data retention mode
With valid VCC applied, the M41T00CAP can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the power input will be switched from the
VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At
this time the clock registers will be maintained by the internal battery supply. On power-up,
when VCC returns to a nominal value, write protection continues for tREC after VCC rises
above VSO .
AI00591
BUS ACTIVITY:
ACK
S
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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