參數(shù)資料
型號(hào): M41T00CAPPC1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, PDIP24
封裝: ROHS COMPLIANT, PLASTIC, DIP-24
文件頁(yè)數(shù): 27/27頁(yè)
文件大?。?/td> 224K
代理商: M41T00CAPPC1
M41T00CAP
Operation
3
Operation
The M41T00CAP clock operates as a slave device on the I2C serial bus. Access is obtained
by implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1.
Seconds register
2.
Minutes register
3.
Century/hours register
4.
Day register
5.
Date register
6.
Month register
7.
Year register
8.
Calibration register
The M41T00CAP clock continually monitors VCC for an out-of-tolerance condition. Should
VCC fall below VPFD, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent erroneous
data from being written to the device from a an out-of-tolerance system. Once VCC falls
below the switchover voltage (VSO), the device automatically switches over to the battery
and powers down into an ultra-low current mode of operation to prolong battery life. If VBAT
is less than VPFD, the device power is switched from VCC to VBAT when VCC drops below
VBAT. If VBAT is greater than VPFD, the device power is switched from VCC to VBAT when VCC
drops below VPFD. Upon power-up, the device switches from battery to VCC at VSO. When
VCC rises above VPFD, the inputs will be recognized.
For more information on battery storage life refer to application note AN1012.
3.1
Wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
3.2
Bus not busy
Both data and clock lines remain high.
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參數(shù)描述
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