參數(shù)資料
型號(hào): M41T00
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: 0.150 INCH, PLASTIC, SO-8
文件頁(yè)數(shù): 12/15頁(yè)
文件大?。?/td> 96K
代理商: M41T00
Symbol
Parameter
Min
Max
Unit
tPD
SCL and SDA at VIH before Power Down
0
ns
tREC
SCL and SDA at VIH after Power Up
10
s
Note: 1. VCC fall time should not exceed 5mV/
s.
Table 9. Power Down/Up Mode AC Characteristics (1)
(TA = –40 to 85
°C)
AI00596
VCC
tREC
tPD
VSO
SDA
SCL
DON'T CARE
Figure 5. Power Down/Up Mode AC Waveforms
2-WIRE BUS CHARACTERISTICS (cont’d)
Acknowledge. Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver, whereas
the master generates an extra acknowledge re-
lated clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is a stable Low during
the High period of the acknowledge related clock
pulse. Of course, setup and hold times must be
taken into account. A master receiver must signal
an end-of-data to the slave transmitter by not gen-
erating an acknowledge on the last byte that has
been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
6/15
M41T00
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