參數(shù)資料
型號(hào): M41ST87WMX6
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOX-28
文件頁數(shù): 19/52頁
文件大?。?/td> 689K
代理商: M41ST87WMX6
Operating modes
M41ST87Y, M41ST87W
Doc ID 9497 Rev 8
2.7
Tamper detection operation
The tamper pins are triggered based on the state of an external switch. Two switch mode
options are available, normally open or normally closed, based on the setting of the tamper
connect mode bit (TCMX). If the selected switch mode is normally open (TCMX = '1'), the
tamper pin will be triggered by being connected to VSS (if the TPMX bit is set to '0') or to VCC
(if the TPMX bit is set to '1'), through the closing of the external switch. When the external
switch is closed, the tamper bit (TBx) will be immediately set, allowing the user to determine
if the device has been physically tampered with. If the selected switch mode is normally
closed (TCMX = '0'), the tamper pin will be triggered by being pulled to VSS or to VOUT
(depending on the state of the TPMX bit), through an internal pull-up/pull-down resistor as a
result of opening the external switch.
When a tamper event occurs, the tamper bits (TB1 and/or TB2) will be immediately set if
TEBX = '1.'
If the tamper interrupt enable bit (TIEX) is set to a '1,' the IRQ/OUT pin will also be activated.
The IRQ/OUT output is cleared by a READ of the flags register (as seen in Figure 24 on
page 34), a reset of the TIE bit to '0,' or the RST output is asserted.
Note:
In order to avoid an inadvertent activation of the IRQ/OUT pin due to a prior tamper event,
the flag register (0Fh) should be read prior to resetting the TEBX bit.
The tamper bits are “read only” bits and are reset only by writing the tamper enable bit
(TEBX) to '0.' Thus, when servicing a tamper interrupt, the user should read the flags
register to clear the IRQ pin, then clear the TEBx bit to clear the TBx flag, followed by setting
TEBx to again enable the tamper circuit.
The tamper detect function operates both under normal power, and in battery backup. Even
if the trigger event occurs during a power-down condition, the tamper flag bit(s) will be set
correctly.
2.8
Sampling
As the switch mode normally closed (TCMX = '0') requires a greater amount of current to
maintain constant monitoring, the M41ST87Y/W offers a programmable tamper detect
sampling bit (TDSX) to reduce the current drawn on VCC or VBAT (see Figure 17 on
page 23). When enabled, the sampling frequency is once per second (1Hz), for a duration of
approximately 1 ms.
When TEBX is disabled, no current will be drawn by the tamper detection circuit. After a
tamper event has been detected, no additional current will be drawn.
Note:
The oscillator must be running for tamper detection to operate in the sampling mode. If the
oscillator is stopped, the tamper detection circuit will revert to constant monitoring.
Note:
Sampling in the tamper high mode (TPMX = '1') may be bypassed while on VCC by
connecting the TPxIN pin to VCC through an external resistor. This will allow constant
monitoring when VCC is “on” and revert to sampling when in battery backup (see Figure 14
相關(guān)PDF資料
PDF描述
M41ST87YMX6 1 TIMER(S), REAL TIME CLOCK, PDSO28
M41ST87YMX6TR 1 TIMER(S), REAL TIME CLOCK, PDSO28
M41ST87WMX6TR 1 TIMER(S), REAL TIME CLOCK, PDSO28
M41ST95WMX6 1 TIMER(S), REAL TIME CLOCK, PDSO28
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M41ST87WSS6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM
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