參數(shù)資料
型號(hào): M41ST85WMX6E
廠商: 意法半導(dǎo)體
英文描述: 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor
中文描述: 3.0/3.3V的I2C串行時(shí)鐘組合,NVRAM中監(jiān)督員和微處理器監(jiān)控
文件頁(yè)數(shù): 22/34頁(yè)
文件大?。?/td> 226K
代理商: M41ST85WMX6E
M41ST85W
22/34
t
rec
Bit
Bit D7 of Clock Register 04h contains the t
rec
Bit
(TR). t
rec
refers to the automatic continuation of
the deselect time after V
CC
reaches V
PFD
. This al-
lows for a voltage settling time before WRITEs
may again be performed to the device after a pow-
er-down condition. The t
rec
Bit will allow the user to
set the length of this deselect time as defined by
Table 6.
.
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watch-
dog Register, FT, AFE, ABE, SQWE, and TR. The
following bits are set to a '1' state: ST, OUT, and
HT (see
Table 7.
).
Table 6. t
rec
Definitions
Note: 1. Default Setting
Table 7. Default Values
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
t
rec
Bit (TR)
STOP Bit (ST)
t
rec
Time
Units
Min
Max
0
0
96
98
ms
0
1
40
200
(1)
ms
1
X
50
2000
μs
Condition
TR
ST
HT
Out
FT
AFE
ABE
SQWE
WATCHDOG
Register
(1)
Initial Power-up
(2)
0
1
1
1
0
0
0
0
0
Subsequent Power-up (with
battery back-up)
(3)
UC
UC
1
UC
0
0
0
0
0
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