參數(shù)資料
型號: M41ST85WMH
廠商: 意法半導(dǎo)體
英文描述: 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR
中文描述: 5.0或3.0V,512位64 × 8串行時(shí)鐘和NVRAM督導(dǎo)員
文件頁數(shù): 14/33頁
文件大?。?/td> 464K
代理商: M41ST85WMH
M41ST85Y, M41ST85W
14/33
Figure 15. Alternate READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 16, page 14. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
13, page 13) and again after it has received the
word address and each data byte.
Figure 16. WRITE Mode Sequence
AI00895
BUS ACTIVITY:
A
S
A
A
A
N
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
A
S
A
A
A
A
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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