參數(shù)資料
型號(hào): M41ST85WMH
廠商: 意法半導(dǎo)體
英文描述: 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR
中文描述: 5.0或3.0V,512位64 × 8串行時(shí)鐘和NVRAM督導(dǎo)員
文件頁數(shù): 10/33頁
文件大?。?/td> 464K
代理商: M41ST85WMH
M41ST85Y, M41ST85W
10/33
OPERATING MODES
The M41ST85Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con-
tained in the device can then be accessed sequen-
tially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
The M41ST85Y/W clock continually monitors V
CC
for an out-of-tolerance condition. Should V
CC
fall
below V
PFD
, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
CC
falls below V
SO
, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
V
CC
rises above V
SO
, the battery is disconnected,
and the power supply is switched to external V
CC
.
Write protection continues until V
CC
reaches
V
PFD
(min) plus t
REC
(min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy.
Both data and clock lines remain
High.
Start data transfer.
A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer.
A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
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M41ST85WMH6E 功能描述:實(shí)時(shí)時(shí)鐘 Serial 512 (64x8) RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
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M41ST85WMH6F-CUT TAPE 制造商:ST 功能描述:M41ST Series 3.3 V I2C Serial RTC NVRAM / Microprocessor Superviser - SOH-28
M41ST85WMH6TR 功能描述:實(shí)時(shí)時(shí)鐘 Advanced Analog RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube