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參數(shù)資料
| 型號(hào)： | M41ST84 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5.0 OR 3.0V, 512 bit (64 x 8) Serial RTC with supervisory functions(具有監(jiān)控功能的5.0V或3.0V，512位(64 x 8)串行RTC) |
| 中文描述： | 5.0或3.0V，512位（64 × 8）（具有監(jiān)控功能的5.0V或3.0V，512位（64 × 8）串行時(shí)鐘監(jiān)督職能的串行時(shí)鐘） |
| 文件頁數(shù)： | 9/31頁 |
| 文件大?。?/td> | 181K |
| 代理商： | M41ST84 |
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M41ST84Y, M41ST84W
OPERATING MODES
The M41ST84Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con-
tained inthe device canthen beaccessed sequen-
tially in the following order:
1.
Tenths/Hundredths of a Second Register
2.
Seconds Register
3.
Minutes Register
4.
Century/Hours Register
5.
Day Register
6.
Date Register
7.
Month Register
8.
Year Register
9.
Control Register
10.
Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20.
Square Wave Register
21 - 64. User RAM
The M41ST84Y/W clock continually monitors V
CC
for an out-of tolerance condition. Should V
CC
fall
below V
PFD
, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
CC
falls below V
SO
, the device automati-
cally switches over to the battery and powers
down intoan ultra low current mode of operationto
conserve batterylife.As systempower returns and
V
CC
rises above V
SO
, the battery is disconnected,
and the power supply is switched to external V
CC
.
Write protection continues until V
CC
reaches
V
PFD
(min) plus t
REC
(min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different IC’s.It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both theSDA and SCLlines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfermay beinitiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy.
Both data and clock lines remain
High.
Start data transfer.
A change in the state of the
data line, from Highto Low, while the clock is High,
defines the START condition.
Stop data transfer.
A change in the state of the
data line, from Lowto High, while the clock is High,
defines the STOP condition.
Data Valid.
The state of the data line represents
valid datawhen after a start condition, the dataline
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
Acknowledge.
Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in sucha way that the SDA lineis a stable Lowdur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be takeninto account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has beenclocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
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| M41ST85WMX6E | 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor |
| M41ST85WMX6F | 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor |
| M41ST95W | 5.0 or 3.0V, 512 bit (64 bit x8) Serial RTC (SPI) SRAM and NVRAM Supervisor(5.0/3.0V, 512位(64位x8)串行RTC(SPI) SRAM和NVRAM監(jiān)控電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST84W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
| M41ST84W_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.0/3.3 V I2C serial RTC with 44 bytes of NVRAM and supervisory functions |
| M41ST84WMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
| M41ST84WMH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
| M41ST84WMH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
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