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參數(shù)資料
| 型號： | M4-128N/64-7JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 7.5 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M4-128N/64-7JC |
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MACH 4 Family
3
GENERAL DESCRIPTION
The MACH 4 family from Lattice offers an exceptionally exible architecture and delivers a
superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products
and software tools. The overall benets for users are a guaranteed and predictable CPLD
solution, faster time-to-market, greater exibility and lower cost. The MACH 4 devices offer
densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention.
The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing also allows product testability on automated test
equipment for device connectivity.
All MACH 4 family members deliver First-Time-Fit and easy system integration with pin-out
retention after any design change and ret. For both 3.3-V and 5-V operation, MACH 4 products
can deliver guaranteed xed timing as fast as 7.5 ns tPD and 111 MHz fCNT through the
SpeedLocking feature when using up to 20 product terms per output (Table 2).
Note:
1. C = Commercial,
I = Industrial
The MACH 4 family offers numerous density-I/O combinations in Thin Quad Flat Pack (TQFP),
Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), and Ball Grid Array (BGA)
packages ranging from 44 to 256 pins (Table 3). It also offers I/O safety features for mixed-
voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive
3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable power-
down mode for extra power savings and individual output slew rate control for the highest speed
transition or for the lowest noise transition.
Table 2. MACH 4 Speed Grades
Device
Speed Grade1
-7
-10
-12
-14
-15
-18
M4-32/32
M4LV-32/32
C
C, I
I
C
I
M4-64/32
M4LV-64/32
C
C, I
I
C
I
M4-96/48
M4LV-96/48
C
C, I
I
C
I
M4-128/64
M4LV-128/64
C
C, I
I
C
I
M4-128N/64
M4LV-128N/64
C
C, I
I
C
I
M4-192/96
M4LV-192/96
C
C, I
I
C
I
M4-256/128
M4LV-256/128
C
C, I
I
C
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M4-192/96-12VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-192/96-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-12VI48 | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-15JC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-15VC | High Performance E 2 CMOS In-System Programmable Logic |
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