參數(shù)資料
型號(hào): M393T2950CZA-CD5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC
中文描述: 注冊的DDR2 SDRAM內(nèi)存模塊240針腳注冊模塊的512MB的基于C -死72位ECC
文件頁數(shù): 20/21頁
文件大?。?/td> 476K
代理商: M393T2950CZA-CD5
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
CK0
CK0
PLL
OUT1
OUTN
Reg.A
Reg.B
Feedback In
Feedback Out
IN
0ns (nominal)
C
120 ohms
120 ohms
120 ohms
120 ohms
C
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
DDR2 SDRAM
DDR2 SDRAM
240 Pin DDR2 Registered DIMM Clock Topology
相關(guān)PDF資料
PDF描述
M393T5750CZA-CD5 DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC
M393T5750CZ3-CCC 40 characters x 2 Lines, 5x7 Dot Matric Character and Cursor
M393T2953CZ3-CD5 40 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor
M393T2950CZ3-CD5 40 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor
M393T5750CZ3-CD5 40 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor
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