參數資料
型號: M390S6450CT1-C7C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD
中文描述: 64Mx72 SDRAM的內存與鎖相環(huán)
文件頁數: 8/12頁
文件大?。?/td> 220K
代理商: M390S6450CT1-C7C
M390S6450CT1
PC133 Registered DIMM
Rev. 0.2 Sept. 2001
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter
Symbol
-7C
-7A
Unit
Note
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
7.5
1000
ns
1
CAS latency=2
7.5
10
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
5.4
ns
1,2
CAS latency=2
5.4
6
Output data
hold time
CAS latency=3
t
OH
3
3
ns
2
CAS latency=2
3
3
CLK high pulse width
t
CH
2.5
2.5
ns
3
CLK low pulse width
t
CL
2.5
2.5
ns
3
Input setup time
t
SS
1.5
1.5
ns
3
Input hold time
t
SH
0.8
0.8
ns
3
CLK to output in Low-Z
t
SLZ
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
5.4
ns
CAS latency=2
5.4
6
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
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