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參數(shù)資料
| 型號： | M38K29RFS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, CPGA100 |
| 封裝： | 0.65 MM PITCH, PGA-100 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 1451K |
| 代理商： | M38K29RFS |
38K2 Group
Rev.3.00
Oct 15, 2006
page 21 of 147
REJ03B0193-0300
SERIAL INTERFACE
Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register (bit 6 of ad-
dress 0FE016) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the Trancemit/Receive buffer register.
Fig. 18 Block diagram of clock synchronous serial I/O
Fig. 19 Operation of clock synchronous serial I/O function
P42/EXTC/SCLK
P43/EXA1/SRDY
P40/EXDREQ/RxD
System clock
1/4
F/F
Serial I/O status register
Serial I/O control register
Receive buffer register
Address 002616
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 0FE216
BRG count source selection bit
Clock control circuit
Falling-edge detector
Data bus
Address 002616
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 002716
Data bus
Address 0FE016
Transmit buffer register
Transmit shift register
P41/EXDACK/TxD
Receive enable signal SRDY
D7
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output
TXD
Serial input
RXD
Write signal to receive/transmit
buffer register (address 002616)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
D7
D0
D1
D2
D3
D4
D5
D6
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