參數(shù)資料
型號： M38K29F8LFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 74/151頁
文件大?。?/td> 1403K
代理商： M38K29F8LFP
38K2 Group
Rev.3.00
Oct 15, 2006
page 29 of 147
REJ03B0193-0300
USB Interrupt Function
USB Interrupt Control Circuit (USBINTCON) has 3 requests and
22 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.
Table 7 USB interrupt sources
Interrupt request bit
(IREQ1: Address 003C16)
USB bus reset
USB interrupt bit
(USBIREQ: Address 001716)
—
Interrupt source
At USB bus reset signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 2.5
s SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)
At SOF packet receive:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)
At Endpoint 00 data transfer complete:
Buffer ready (read/write enabled state)
Control transfer completed
Status stage transition
SETUP buffer ready (read enabled state)
Control transfer error
At Endpoint 01 data transfer complete:
Buffer 0 ready (read/write enabled state)
Buffer 1 ready (read/write enabled state)
Transfer error
At Endpoint 02 data transfer complete:
Buffer 0 ready (read/write enabled state)
Buffer 1 ready (read/write enabled state)
Transfer error
At Endpoint 03 data transfer complete:
Buffer 0 ready (read/write enabled state)
Buffer 1 ready (read/write enabled state)
Transfer error
At Endpoint 10 data transfer complete:
Buffer ready (read/write enabled state)
Control transfer completed
Status stage transition
SETUP buffer ready (read enabled state)
Control transfer error
At Endpoin 11 data transfer complete:
Buffer 0 ready (write enabled state)
At suspend signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)
At resume signal detection:
After enabling the USB module (USBE = “1”) and resume interrupt (RSME
= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.
USB SOF
—
USB device
EP00
EP01
EP02
EP03
EP10
EP11
SUS
RSM
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