參數(shù)資料
型號： M38K29F8LFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 132/151頁
文件大?。?/td> 1403K
代理商： M38K29F8LFP
38K2 Group
Rev.3.00
Oct 15, 2006
page 81 of 147
REJ03B0193-0300
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
Fig. 122 CPU channel receiving operation
Address ExA0
Chip select ExCS
A0 = “1”
CS = “0”
A0 = “1”
CS = “0”
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock
φ
Interrupt request ExINT
[RxB_RDY]
RxB_RDY
Receive buffer full bit RXB_FULL
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
CPU channel receive enable bit
RXB_ENB
Receive buffer read
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)
Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.
If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:
The data is written into the receive buffer (RXBUF)
Negation of the receive buffer ready signal (RxB_RDY) to an external is made
The RXB_FULL interrupt is generated.
When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.
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相關代理商/技術參數(shù)
參數(shù)描述
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M38K29F8LHP#UO 制造商:Renesas Electronics Corporation 功能描述:
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M38K29T-PAC 制造商:Renesas Electronics Corporation 功能描述:DEV SIMPLE TOOL SYSTEM PKG FOR 38000/38K - Bulk
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