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38K0 Group User’s Manual
List of figures
Fig. 96 Memory channel receiving operation (3) ................................................................... 1-68
Fig. 97 Memory channel tranmitting operation (1) ................................................................. 1-69
Fig. 98 Memory channel tranmitting operation (2) ................................................................. 1-70
Fig. 99 Multichannel RAM timing diagram (no wait) ............................................................. 1-71
Fig. 100 Multichannel RAM timing diagram (one wait) ......................................................... 1-71
Fig. 101 Multichannel RAM operation example ...................................................................... 1-72
Fig. 102 Structure of A-D control register .............................................................................. 1-73
Fig. 103 10-bit A-D mode reading ........................................................................................... 1-73
Fig. 104 A-D converter block diagram .................................................................................... 1-74
Fig. 105 Block diagram of Watchdog timer ............................................................................ 1-75
Fig. 106 Structure of Watchdog timer control register .......................................................... 1-75
Fig. 108 Reset sequence .......................................................................................................... 1-76
Fig. 107 Example of reset circuit ............................................................................................. 1-76
Fig. 109 Block diagram of PLL circuit ..................................................................................... 1-77
Fig. 110 Structure of PLL control register .............................................................................. 1-78
Fig. 111 Ceramic resonator or quartz-crystal oscilltor circuit .............................................. 1-80
Fig. 112 External clock input circuit ........................................................................................ 1-80
Fig. 114 System clock generating circuit block diagram (single-chip mode) ..................... 1-80
Fig. 113 Structure of MISRG .................................................................................................... 1-80
Fig. 115 State transitions of clock ........................................................................................... 1-81
Fig. 116 Block diagram of built-in flash memory ................................................................... 1-83
Fig. 117 Structure of flash memory control register .............................................................. 1-84
Fig. 118 CPU rewrite mode set/release flowchart ................................................................. 1-85
Fig. 119 Program flowchart ....................................................................................................... 1-87
Fig. 120 Erase flowchart ........................................................................................................... 1-88
Fig. 121 Full status check flowchart and remedial procedure for errors ........................... 1-90
Fig. 122 Structure of ROM code protect control register ..................................................... 1-91
Fig. 123 ID code store addresses ........................................................................................... 1-92
Fig. 124 Pin connection diagram in standard serial I/O mode (1) ...................................... 1-96
Fig. 125 Timing for page read .................................................................................................. 1-98
Fig. 126 Timing for reading status register ............................................................................ 1-98
Fig. 127 Timing for clear status register ................................................................................. 1-99
Fig. 128 Timing for page program ........................................................................................... 1-99
Fig. 129 Timing for erase all blocks ...................................................................................... 1-100
Fig. 130 Timing for download ................................................................................................. 1-101
Fig. 131 Timing for version information output .................................................................... 1-102
Fig. 132 Timing for Boot ROM area output .......................................................................... 1-102
Fig. 133 Timing for ID check .................................................................................................. 1-103
Fig. 134 ID code storage addresses ..................................................................................... 1-103
Fig. 135 Full status check flowchart and remedial procedure for errors ......................... 1-106
Fig. 136 Example circuit application for standard serial I/O mode ................................... 1-107
Fig. 137 Definition of A-D conversion accuracy ................................................................... 1-109
Fig. 138 A-D conversion equivalent circuit ........................................................................... 1-112
Fig. 139 A-D conversion timing chart .................................................................................... 1-112