參數(shù)資料
型號: M38D24G4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 77/138頁
文件大?。?/td> 2880K
代理商: M38D24G4-XXXFP
Rev.3.02
Apr 10, 2008
Page 41 of 131
REJ03B0177-0302
38D2 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 33 Block diagram of UART serial I/O
Fig. 34 Operation of UART serial I/O function
1/4
OE
PE FE
1/16
Data bus
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
Transmit buffer register
Data bus
Transmit shift register
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
UART control register
Character length selection bit
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O status register
Serial I/O control register
P54/RXD1
[P33/RXD2]
P56/SCLK1
[P31/SCLK2]
P55/TXD1
[P32/TXD2]
Address 001816
[Address 001D16]
Address 001C16 [Address 0FE216]
Address 001816
[Address 001D16]
Address 001916
[Address 001E16]
Address 001A16
[Address 001F16]
Address 001B16
[Address 0FE116]
[ ] : For Serial I/O2
φ SOURCE: represents the supply source of internal clock φ.
XIN input: in the frequency/2, 4 or 8 mode,
Internal on-chip oscillator divided by 4 in the on-chip
oscillator mode, and Sub clock in the low-speed mode.
φSOURCE
SP detector
ST/SP/PA generator
ST detector
TSC=0
TBE=1
RBF=0
TBE=0
RBF=1
ST
D0
D1
SP
D0
D1
ST
SP
TBE=1
TSC=1
ST
D0
D1
SP
D0
D1
ST
SP
Serial input RxD
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting
of the transmit interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC flag = “1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until
changing to TSC flag = “0”.
Transmit or receive clock
Transmit buffer register
write signal
Serial output TxD
Receive buffer register
read signal
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