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- 您現(xiàn)在的位置:買賣IC網(wǎng) > PDF目錄45048 > M38D24G4-XXXFP 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
型號(hào):
M38D24G4-XXXFP
元件分類:
微控制器/微處理器
英文描述:
8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝:
14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù):
75/138頁(yè)
文件大?。?/td>
2880K
代理商:
M38D24G4-XXXFP
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Rev.3.02Apr 10, 2008Page 39 of 131REJ03B0177-030238D2 Group<Notes on Timer Y> CNTR1 Interrupt Active Edge SelectionCNTR1 interrupt active edge depends on the CNTR1 active edgeswitch bit. However, in pulse width HL continuouslymeasurement mode, CNTR1 interrupt request is generated atboth rising and falling edges of CNTR1 pin input signalregardless of the setting of CNTR1 active edge switch bit. Timer Y Read/Write Control When reading from/writing to timer Y, read from/write to boththe high-order and low-order bytes of timer Y. When the valueis read, read the high-order bytes first and the low-order bytesnext. When the value is written, write the low-order bytes firstand the highorder bytes next.Write to or read from the timer X register in 16-bit units. Ifreading from the timer Y register during write operation orwriting to it during read operation is performed, normaloperation will not be performed. Which write control can be selected by the timer Y writecontrol bit (b0) of the timer Y control register (address003916), writing data to both the latch and the timer at thesame time or writing data only to the latch. When writing avalue to the timer Y address to write to the latch only, thevalue is set into the reload latch and the timer is updated at thenext underflow. After reset release, when writing a value to thetimer Y address, the value is set into the timer and the timerlatch at the same time, because they are set to write at the sametime.When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost thesame, the value is set into the timer and the timer latch at thesame time. In this time, counting is stopped during writing tothe high-order reload latch. This also applies when the frequency divider output is selectedas the timer count source and the count source is switched inconjunction with a transition between operating modes (on-chip oscillator mode, XIN mode, or low-speed mode). Becareful when changing settings in the CPU mode register.Fig. 30 Structure of timer Y related registersb7b0Timer Y control register(TYCON: address 003916)Timer Y write control bit0 : Write data to both timer latch and timer1 : Write data to timer latch onlyTimer Y count source selection bit0 : Frequency divider output1 : f(XCIN)Timer Y frequency division selection bitsb3 b20 0 : 1/16× φSOURCE0 1 : 1/1× φSOURCE1 0 : 1/2× φSOURCE1 1 : 1/256× φSOURCENot used (returns “0” when read)φ SOURCE: represents the supply source of internal clock φ.XIN input: in the frequency/2, 4 or 8 mode,Internal on-chip oscillator divided by 4 in the on-chiposcillator mode, and Sub clock in the low-speed mode.Real time port control bits (P46, P47 )b1 b00 0 : Real time port function invalid0 1 : Do not set1 0 : Do not set1 1 : Real time port function validP46 data for real time portP47 data for real time portTimer Y operating mode bitsb5 b40 0 : Timer mode0 1 : Period measurement mode1 0 : Event counter mode1 1 : Pulse width HL continuous measurement modeCNTR1 active edge switch bit0 : Count at rising edge in event counter modeMeasure falling period in period measurement modeFalling edge active for CNTR1 interrupt1 : Count at falling edge in event counter modeMeasure rising period in period measurement modeRising edge active for CNTR1 interruptTimer Y count stop bit0 : Count operation1 : Count stopTimer Y mode register(TYM: address 003816)b0b7
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