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參數(shù)資料
| 型號(hào)： | M38C37ECMFS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQCC80 |
| 封裝： | 0.80 MM PITCH, GLASS SEALED, CERAMIC, LCC-80 |
| 文件頁(yè)數(shù)： | 155/223頁(yè) |
| 文件大?。?/td> | 1698K |
| 代理商： | M38C37ECMFS |
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38C3 Group User’s Manual
HARDWARE
1-23
TIMERS
8-Bit Timer
The 38C3 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
The count can be stopped by setting the stop bit of each timer to “1.”
The system clock
φ can be set to either the high-speed mode or low-
speed mode with the CPU mode register. At the same time, timer
internal count source is switched to either f(XIN) or f(XCIN).
qTimer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 under-
flow signal divided by 2 is output from the P41/T1OUT pin. The wave-
form polarity changes each time timer 1 overflows. The active edge
of the external clock CNTR0 can be switched with the bit 6 of the
interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2 is
set to “0116.”
qTimer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 under-
flow signal divided by 2 is output from the P42/T3OUT pin. The wave-
form polarity changes each time timer 3 overflows. The active edge
of the external clock CNTR1 can be switched with the bit 7 of the
interrupt edge selection register.
qTimer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 under-
flow signal divided by 2 can be output from the P52/PWM1 pin.
qTimer 6 PWM1 Mode
Timer 6 can output a rectangular waveform with “H” duty cycle n/
(n+m) from the P52/PWM1 pin by setting the timer 56 mode register
(refer to Figure 20). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Fig. 18 Structure of timer related register
FUNCTIONAL DESCRIPTION
Timer 12 mode register
(T12M: address 002816)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P41)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1
11 : Not available
Timer 3 output selection bit (P42)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Timer 56 mode register
(T56M: address 002A16)
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/16 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P5 2)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
b7
b0
b7
b0
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