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參數(shù)資料
| 型號(hào)： | M38C37ECMFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 24/65頁 |
| 文件大?。?/td> | 808K |
| 代理商： | M38C37ECMFP |
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27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
LCD DRIVE CONTROL CIRCUIT
The 38C3 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output enable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for a LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
Fig. 27 Structure of LCD related registers
segment output enable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio
1
2
3
4
Maximum number of display pixels
32 dots
or 8 segment LCD 4 digits
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
Segment output enable bit 0
0 : I/O ports P20–P23
1 : Segment output SEG0–SEG3
Segment output enable bit 1
0 : I/O ports P24–P27
1 : Segment output SEG4–SEG7
Segment output enable bit 2
0 : I/O ports P00–P03
1 : Segment output SEG8–SEG11
Segment output enable bit 3
0 : I/O ports P04–P07
1 : Segment output SEG12–SEG15
Segment output enable bit 4
0 : I/O ports P10–P13
1 : Segment output SEG16–SEG19
Segment output enable bit 5
0 : I/O ports P14–P17
1 : Segment output SEG20–SEG23
Segment output enable bit 6
0 : Output ports P30–P33
1 : Segment output SEG24–SEG27
Segment output enable bit 7
0 : Output ports P34–P37
1 : Segment output SEG28–SEG31
Segment output enable register
(SEG : address 003816)
b7
b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits
0 0 : 1 (use COM0)
0 1 : 2 (use COM0,COM1)
1 0 : 3 (use COM0–COM2)
1 1 : 4 (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
b7
b0
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