參數(shù)資料
型號(hào)： M38C24M4-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 34/63頁(yè)
文件大?。?/td> 1000K
代理商： M38C24M4-XXXHP
34
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D CONVERTER
The 38C2 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 001B
16
), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 001A
16
).
During A-D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference volt-
age input pin (V
REF
) can be controlled by the V
REF
input switch bit
(bit 0 of address 001A
16
). When
“
1
”
is written to this bit, the resistor
ladder is always connected to V
REF
. When
“
0
”
is written to this bit,
the resistor ladder is disconnected from V
REF
except during the A-D
conversion.
[A-D Control Register (ADCON)]
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 3 is an AD conversion completion bit and
“
0
”
during A-
D conversion. This bit is set to
“
1
”
upon completion of A-D conversion.
A-D conversion is started by setting
“
0
”
in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AV
SS
and V
REF
, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P4
7
/AN
7
–
P4
0
/
AN
0
and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD conver-
sion interrupt request bit to
“
1.
”
Fig. 31 Block diagram of A-D converter
Fig. 30 Structure of A-D control register
Data bus
AV
SS
A-D interrupt request
b7
b0
3
P4
0
/O
OUT0
/AN
0
P4
1
/O
OUT1
/AN
1
P4
2
/AN
2
P4
3
/AN
3
P4
4
/AN
4
P4
5
/AN
5
P4
6
/AN
6
P4
7
/AN
7
A-D control register
C
Comparator
A-D control circuit
A-D conversion register (H)
A-D conversion register (L)
(Address 001B
16
)
(Address 001A
16
)
Resistor ladder
V
REF
Analog input pin selection bits
b2 b1 b0
0 0 0: P4
0
/AN
0
0 0 1: P4
1
/AN
1
0 1 0: P4
2
/AN
2
0 1 1: P4
3
/AN
3
1 0 0: P4
4
/AN
4
1 0 1: P4
5
/AN
5
1 1 0: P4
6
/AN
6
1 1 1: P4
7
/AN
7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
AD conversion clock selection bits
b5 b4
0 0: Frequency not divided
0 1: Frequency divided by 2
1 0: Frequency divided by 4
1 1: Frequency divided by 8
10-bit or 8-bit conversion switch bit
0: 10-bit AD
1: 8-bit AD
Booster selection bit
0: Booster not used
1: Booster used
A-D control register
(ADCON: address 0019
16
)
b7
b0
10-bit reading
(Read address 001B
16
before 001A
16
)
A-D conversion register 1
(Address 001B
16
)
A-D conversion register 2
(Address 001A
16
)
* V
REF
input switch bit
0: ON only during A-D conversion
8-bit reading
(Read only address 001B
16
)
(Address 001B
16
)
b0
b7
b1
b0
*
b9 b8 b7 b6 b5 b4 b3 b2
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
b7
b0
(high-order)
(low-order)
Note :
The bit 5 to bit 1 of address 001A
16
becomes
“
0
”
at reading.
Also, bit 0 is undefined at reading.
1: ON
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