29
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 24 Block diagram of Timer X, Y
Real time port
control bit
Real time port
control bit
Q D
Latch
Q D
L
a
t
c
h
P4
7
direction
register
P4
7
latch
P4
7
data for real time port
P4
6
direction
register
P4
6
latch
P4
6
data for real time port
“
1
”
Timer Y (low-order) latch (8)
“
0
”
CNTR
1
active
edge switch bit
“
10
”
P
4
7
/
R
T
P
1
/
A
N
7
P4
6
/RTP
0
/AN
6
P6
0
/CNTR
1
Falling edge detection
Period measurement mode
T
r
i
m
q
e
u
r
s
Y
t
i
n
t
e
r
r
u
p
t
e
e
Pulse width HL continuous
measurement mode
Timer Y operating
mode bits
C
i
n
N
t
e
T
r
R
1
r
u
p
t
r
e
q
u
e
s
t
Rising edge detection
Co“
X
c
I
N
1
”
Clock for Timer Y
D
a
t
a
b
u
s
1
/
2
1
/
4
F
d
r
e
v
q
d
u
e
e
r
n
c
y
i
i
N
c
o
l
i
c
s
e
k
s
f
i
e
l
t
l
e
e
r
c
s
t
i
a
o
m
n
p
b
l
i
n
g
o
i
t
“
1
”
“
0
”
T
r
i
e
m
q
e
u
r
s
X
t
i
n
t
e
r
r
u
p
t
e
Equal
“
000
”
“
001
”
“
010
”
“
011
”
“
101
”
P
m
u
e
l
s
n
e
t
m
w
i
o
d
d
t
h
e
m
e
a
s
u
r
e
Timer X count
stop bit
Compare register (low-order)(8) Compare register (high-order)(8)
Output selection bit
P3
5
latch
P3
5
direction
P3
5
/T
XOUT
/(LED
5
)
P
5
1
/
I
N
T
1
P
3
4
/
I
N
T
2
/
(
L
E
D
4
)
S
R
Q
Q
T
T
XOUT
edge
switch bit
S
S
“
0
”
“
1
”
Q
Q
T
Pulse output mode
C
e
N
d
T
e
R
0
s
a
i
c
t
c
t
i
v
e
b
i
g
w
h
t
s
T
m
i
m
o
e
d
r
X
b
t
o
s
p
e
r
a
t
i
n
g
e
i
CNTR
0
interrupt request
“
1
0
0
”
E
x
t
e
n
d
l
a
t
c
h
(
2
)
E
x
t
e
n
d
c
o
u
n
t
e
r
(
2
)
T
i
m
e
c
r
n
X
t
r
w
o
r
i
b
t
e
i
t
o
l
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
D
Q
L
a
t
c
h
Data for control of event counter window
P
3
7
/
C
N
T
R
0
/
(
L
E
D
7
)
P
5
0
/
I
N
T
0
0
μ
s
4/f(X
IN
)
8/f(X
IN
)
16/f(X
IN
)
Delay time
“
00
”
“
01
”
“
10
”
“
11
”
N
(
4
l
e
o
i
t
e
s
i
m
l
e
e
f
i
s
u
l
t
d
e
s
r
a
g
v
m
m
e
e
s
j
n
t
)
IN
i
n
T
0
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Count source selection bit
Xc
IN
C
l
o
c
k
f
o
r
T
i
m
e
r
X
Sy
s
t
e
m
c
F
l
o
r
c
e
k
q
c
u
o
n
e
t
n
r
o
c
l
y
b
i
t
d
s
3
C
l
o
c
k
f
o
r
T
i
m
e
r
Y
X
I
N
R
e
a
l
t
i
m
e
p
o
r
t
“
0
”
c
o
n
t
r
o
l
b
i
t
Timer Y mode register
write signal
Timer Y (low-order)(8)
X
c
I
N
X
I
N
i
v
i
d
e
r
IGBT output mode
Timer Y operating mode bits
“
00
”
,
“
01
”
,
“
10
”
Timer X frequency division
selection bit
Timer Y frequency division
selection bit
3
B
o
d
t
h
t
e
c
d
t
g
o
e
n
s
e
e
i
“
00
”
“
0
1
”
“
1
“
1
0
1
”
”
Edge
detection
T
XOUT
output
control bit 1
T
X
c
o
O
n
U
t
r
T
o
o
b
u
i
t
t
p
2
u
t
l
Timer X
operating
mode bits
“
0
1
0
”
“
00
”
,
“
01
”
,
“
11
”
“
1
”
“
0
”
“
1
”
“
0
”
“
1
”
“
1
1
”
“
0
”
Timer Y write control bit
t
o
p
b
i
t
T
i
m
e
r
Y
c
o
u
n
t
s
“
000
”
“
001
”
“
011
”
“
100
”
“
101
”
Timer X operating
mode bits
“
0
1
0
”
Delay
circuit
Timer Y (high-order) latch (8)
Timer Y (high-order)(8)
Timer X (low-order) latch (8)
Timer X (low-order)(8)
Timer X (high-order) latch (8)
i
m
e
r
X
(
h
i
g
T
h
-
o
r
d
e
r
)
(
8
)
T
t
h
1
h
e
/
1
e
,
c
1
f
o
l
o
/
2
l
l
o
k
,
1
w
/
1
i
o
6
n
r
g
,
1
v
i
/
a
m
3
l
u
e
,
e
r
;
1
s
c
a
n
b
e
s
e
l
e
c
t
e
d
c
f
T
2
/
6
4
,
1
/
1
2
8
,
1
/
2
5
6
,
1
/
1
0
2
4
“
1
”
“
0
”