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參數(shù)資料
| 型號： | M38C13M6-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 955K |
| 代理商： | M38C13M6-XXXHP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
27
A-D CONVERTER
The functional blocks of the A-D converter are described below.
q A-D Converter
The conversion method of this A-D converter is the 8-bit resolution
successive comparison method. This A-D converter has the
ADKEY function for A-D conversion of “L” level analog input to
ADKEY pin automatically.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
After power on or system is released from reset, the value is unde-
fined.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 enables the ADKEY function. Writing “1” to this
bit enables the ADKEY function. When this function is set to be
valid, the analog input pin selection bits are invalid. Also, when the
bit 4 is “1”, do not write “0” to bit 3 by program.
Resistor ladder
The resistor ladder divides the voltage between VCC and VSS by
256, and outputs the comparison voltages to the comparator.
Channel Selector
The channel selector selects one of the input ports AN7–AN0.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The conver-
sion accuracy may be low because the charge is lost if the conver-
sion speed is not enough.
Accordingly, set f(XIN) to at least 500kHz during A-D conversion in
the middle- or high-speed mode.
Also, do not execute the STP and WIT instructions during the A-D
conversion.
In the low-speed mode, since the A-D conversion is executed by
the built-in self-oscillation circuit, the minimum value of f(XIN) fre-
quency is not limited.
Fig. 26 A-D converter block diagram
Fig. 25 Structure of A-D control register
A-D control register
(ADCON : address 003416, initial value: 0816)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Analog input pin selection bits
0 0 0 : AN0
0 0 1 : AN1
0 1 0 : AN2
0 1 1 : AN3
1 0 0 : AN4
1 0 1 : AN5
1 1 0 : AN6
1 1 1 : AN7
ADKEY enable bit (Note)
0 : Disabled
1 : Enabled
b7
b0
Not used (returns “0” when read)
(Do not write “1” to these bits.)
Note: When the ADKEY enable bit is “1”, analog input selection bit is invalid.
Do not execute the A-D conversion while ADKEY is enabled.
Even if ADKEY is enabled, values of bits 0 to 2 of ADCON are not affected.
VSS
b7b0
3
AN0/ADKEY0
AN1/ADKEY1
AN2/ADKEY2
AN3/ADKEY3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
8
ADKEY
control circuit
Comparator
A-D control circuit
A-D interrupt request
Data bus
A-D control register
A-D conversion register
Resistor ladder
C
h
a
n
e
l
s
e
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c
to
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VCC
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