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參數(shù)資料
| 型號(hào)： | M38B79MFH |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 94/109頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | M38B79MFH |
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94
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38B79FF has the CPU reprogramming mode where a built-
in flash memory is handled by the central processing unit (CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 98) and the flash command register (see Figure 99).
The CNV
SS
pin is used as the V
PP
power supply pin in CPU repro-
gramming mode. It is necessary to apply the power-supply voltage
of V
PP
H from the external to this pin.
Functional Outline (CPU reprogramming mode)
Figure 98 shows the flash memory control register bit configura-
tion. Figure 99 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogram-
ming mode select bit. When this bit is set to
“
1
”
and V
PP
H is
applied to the CNVss/V
PP
pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes
“
1
”
during erase and program
execution.
Whether these operations have been completed or not is judged
by checking this flag after each command of erase and the pro-
gram is executed.
Bits 4, 5 of the flash memory control register are the erase/pro-
gram area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Only for the specified area, programming is enabled; for
the other areas, programming is disabled.
Figure 100 shows the CPU mode register bit configuration in the
CPU reprogramming mode.
Fig. 98 Flash memory control register bit configuration
7
6
5
4
3
2
1
0
0
0
Flash memory control regsiter
(FCON : address 0EFE
16
)
CPU reprogramming mode select bit
(Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or V
PP
L to CNV
SS
/V
PP
pin, CPU reprogramming mode is
invalid. When applying V
PP
H to CNV
SS
/V
PP
pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Erase/Program area select bits
0 0 : Addresses 1000
16
to FFFF
16
(total 60 Kbytes)
0 1 : Addresses 1000
16
to 7FFF
16
(total 28 Kbytes)
1 0 : Addresses 8000
16
to FFFF
16
(total 32 Kbytes)
1 1 : Not available
Fix this bit to
“
0
”
.
Fix this bit to
“
0
”
.
Note:
Bit 0 can be reprogrammed only when 0 V is applied to the CNV
SS
/V
PP
pin.
Not used (returns
“
0
”
when read)
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