參數(shù)資料
型號(hào)： M38B79MFH-A154FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 67/109頁(yè)
文件大?。?/td> 1559K
代理商： M38B79MFH-A154FP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
67
X
IN
Data bus
X
CIN
“
1
”
“
0
”
Internal system clock
selection bit
(Note)
“
0
”
“
1
”
1/8
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
STP instruction
Watchdog timer H (8)
“
FF
16
”
is set
when watchdog
timer control
register is written
to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
“
FF
16
”
is set when
watchdog timer
control register is
written to.
1/2
(2) Watchdog timer H count source selection
bit operation
Bit 7 of the watchdog timer control register (address 0EEE
16
) per-
mits selecting a watchdog timer H count source. When this bit is
set to
“
0
”
, the underflow signal of watchdog timer L becomes the
count source. The detection time is set to 131.072 ms at f(X
IN
) = 4
MHz frequency, and 32.768 s at f(X
CIN
) = 32 kHz frequency.
When this bit is set to
“
1
”
, the count source becomes the signal di-
vided by 8 for f(X
IN
) or divided by 16 for f(X
CIN
). The detection
time in this case is set to 512
μ
s at f(X
IN
) = 4 MHz frequency, and
128 ms at f(X
CIN
) = 32 kHz frequency.
This bit is cleared to
“
0
”
after reset.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0EEE
16
) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is
“
0
”
, the STP instruction is enabled.
When this bit is
“
1
”
, the STP instruction is disabled.
If the STP instruction is executed, an internal resetting occurs.
When this bit is set to
“
1
”
, it cannot be rewritten to
“
0
”
by program.
This bit is cleared to
“
0
”
after reset.
I
Note
When releasing the stop mode, the watchdog timer performs its
count operation even in the stop release waiting time. Be careful
not to cause the watchdog timer H to underflow in the stop release
waiting time, for example, by writing any data in the watchdog
timer control register (address 0EEE
16
) before executing the STP
instruction.
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway). The watchdog timer consists of an
8-bit watchdog timer L and a 8-bit watchdog timer H.
Standard Operation Of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 0EEE
16
) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register and an in-
ternal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register may be started before an un-
derflow. When the watchdog timer control register is read, the
values of the high-order 6 bits of the watchdog timer H, STP in-
struction disable bit, and watchdog timer H count source selection
bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
0EEE
16
), a watchdog timer H is set to
“
FF
16
”
and a watchdog
timer L to
“
FF
16
”
.
Fig. 73 Structure of watchdog timer control register
Fig. 72 Block diagram of watchdog timer
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/8 or f(X
CIN
)/16
Watchdog timer H (for read-out of high-order 6 bits)
Watchdog timer control register
(WDTCON : address 0EEE
16
)
b7
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