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38B5 Group User’s Manual
List of figures
Fig. 3.5.39 Structure of interrupt request register 2 ...............................................................3-55
Fig. 3.5.40 Structure of interrupt control register 1 ................................................................3-56
Fig. 3.5.41 Structure of interrupt control register 2 ................................................................3-57
Fig. 3.5.42 Structure of pull-up control register 1...................................................................3-58
Fig. 3.5.43 Structure of pull-up control register 2...................................................................3-58
Fig. 3.5.44 Structure of P1FLDRAM write disable register....................................................3-59
Fig. 3.5.45 Structure of P3FLDRAM write disable register....................................................3-60
Fig. 3.5.46 Structure of FLDC mode register ..........................................................................3-61
Fig. 3.5.47 Structure of Tdisp time set register ......................................................................3-62
Fig. 3.5.48 Structure of Toff1 time set register .......................................................................3-63
Fig. 3.5.49 Structure of Toff2 time set register .......................................................................3-63
Fig. 3.5.50 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-64
Fig. 3.5.51 Structure of port P0FLD/Port switch register .......................................................3-64
Fig. 3.5.52 Structure of port P2FLD/port switch register .......................................................3-65
Fig. 3.5.53 Structure of port P8FLD/port switch register .......................................................3-65
Fig. 3.5.54 Structure of port P8FLD output control register.................................................. 3-66
Fig. 3.5.55 Structure of buzzer output control register...........................................................3-66
Fig. 3.12.1 Pin configuration of M35501FP..............................................................................3-91
Fig. 3.12.2 Functional block diagram ........................................................................................3-92
Fig. 3.12.3 Port block diagram...................................................................................................3-93
Fig. 3.12.4 Digit setting...............................................................................................................3-94
Fig. 3.12.5 16-digit mode output waveform..............................................................................3-95
Fig. 3.12.6 Optional digit mode output waveform ...................................................................3-95
Fig. 3.12.7 Cascade mode connection example: 17 digits or more selected ..................... 3-96
Fig. 3.12.8 Cascade mode output waveform ........................................................................... 3-96
Fig. 3.12.9 Connection example with 38B5 Group microcomputer (1 to 16 digits) ...........3-97
Fig. 3.12.10 Connection example with 38B5 Group microccomputer (17 to 32 digits) ..... 3-97
Fig. 3.12.11 Digit output waveform when reset signal is input .............................................3-98
Fig. 3.12.12 Power-on reset circuit ........................................................................................... 3-99
Fig. 3.12.13 Timing diagram.....................................................................................................3-102