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參數(shù)資料
| 型號： | M38B57MCH-P202FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | RES,Carbon Film,51Ohms,350WV,5+/-% Tol |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 53/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B57MCH-P202FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
53
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Fig. 62 Structure of Watchdog Timer Control Register
“0,” the underflow signal of watchdog timer L becomes the count
source. The detection time is set then to f(X
IN
) = 2.1 s at 4 MHz
frequency and f(X
CIN
) = 512 s at 32 kHz frequency.
When this bit is set to “1,” the count source becomes the signal
divided by 8 for f(X
IN
) (or divided by 16 for f(X
CIN
)). The detection
time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and
f(XCIN) = 2 s at 32 KHz frequency. This bit is cleared to “0” after
resetting.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 002B
16
) permits
disabling the STP instruction when the watchdog timer is in opera-
tion.
When this bit is “0,” the STP instruction is enabled.
When this bit is “1,” the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1,” it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
I
Note
When releasing the stop mode, the watchdog timer performs its count
operation even in the stop release waiting time. Be careful not to
cause the watchdog timer H to underflow in the stop release waiting
time, for example, by writing data in the watchdog timer control reg-
ister (address 002B
16
) before executing the STP instruction.
Fig. 61 Block Diagram of Watchdog Timer
X
IN
Data bus
X
CIN
“1”
“0”
Internal system clock
(Note)
“0”
“1”
1/8
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
STP instruction
Watchdog timer H (12)
16
” is set
“FFF
timer control
to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
“FF
16
” is set when
watchdog timer
1/2
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/8 or f(X
CIN
)/16
Watchdog timer H (for read-out of high-order 6 bit)
Watchdog timer control register
(WDTCON : address 002B
16
)
b7
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software runaway). The watchdog timer consists of an 8-bit watch-
dog timer L and a 12-bit watchdog timer H.
G
Standard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 002B
16
) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 002B
16
) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 002B
16
) may be started
before an underflow. When the watchdog timer control register
(address 002B
16
) is read, the values of the 6 high-order bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
002B
16
), a watchdog timer H is set to “FFF
16
” and a watchdog timer
L to “FF
16
.”
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 002B
16
) permits
selecting a watchdog timer H count source. When this bit is set to
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