參數(shù)資料
型號(hào): M38B52E5XXXFS
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 36/70頁(yè)
文件大?。?/td> 864K
代理商: M38B52E5XXXFS
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
40
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Data setup
(1) 16-timingOrdinary Mode
The area of addresses 0FB016 to 0FFF16 are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB016,
the last data of FLD port P0 is stored at address 0FC016,
the last data of FLD port P1 is stored at address 0FD016,
the last data of FLD port P3 is stored at address 0FE016,
and the last data of FLD port P8 is stored at address 0FF016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB016, 0FC016, 0FD016, 0FE016, and
0FF016.
Set the FLD data pointer reload register to the value given by the
number of digits – 1. “1” is always written to bit 6, and “0” is
always written to bit 5. Note that “0” is always read from bits 6
and 5 when reading.
(2) 16-timingGradation Display Mode
Display data setting is performed in the same way as that of the
16-timingordinary mode. Gradation display control data is
arranged at an address resulting from subtracting 005016 from
the display data store address of each timing and pin. Bright dis-
play is performed by setting “0,” and dark display is performed by
setting “1.”
(3) 32-timing Mode
The area of addresses 0F6016 to 0FFF16 are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0F6016,
the last data of FLD port P0 is stored at address 0F8016,
the last data of FLD port P1 is stored at address 0FA016,
the last data of FLD port P3 is stored at address 0FC016,
and the last data of FLD port P8 is stored at address 0FE016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0F6016, 0F8016, 0FA016, 0FC016, and
0FE016.
Set the FLD data pointer reload register to the value given by the
number of digits–1. “1” is always written to bit 6, and “0” is always
written to bit 5. Note that “0” is always read from bits 6 and 5
when reading.
Fig. 43 Example of Using the FLD Automatic Display RAM in
16-timingOrdinary Mode
Number of FLD segments: 15
Number of timing: 8
(FLD data pointer reload register = 7)
Address
0FCF16
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FE016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
0FF016
0FB016
The last timing
(The last data of FLDP2)
7
654
3210
Bit
The last timing
(The last data of FLDP0)
The last timing
(The last data of FLDP1)
The last timing
(The last data of FLDP3)
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP8)
FLDP8 data area
Note:
shaded area is used for segment.
shaded area is used for digit.
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