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| 型號： | M38B52E5XXXFS |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 24/70頁 |
| 文件大?。?/td> | 864K |
| 代理商： | M38B52E5XXXFS |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
29
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
When the external synchronous clock is selected, input an “H” level
_________
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 be-
come valid, enabling a transmit/receive operation, while an “L” level
signal is input into the SBUSY1 input and an “H” level signal is input
__________
into the SBUSY1 input.
__________
When changing the input values in the SBUSY1 input and the SBUSY1
input at these operations, change them when the SCLK1 input is in a
high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, en-
abling serial transfer by inputting a transfer clock to SCLK1, while an
“L” level signal is input into the SBUSY1 input and an “H” level signal
__________
is input into the SBUSY1 input.
3. SBUSY1 output signal
The SBUSY1 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the SBUSY1 output is to be active at trans-
fer of each 1-byte data or during transfer of all data can be selected
by the SBUSY1 output SSTB1 output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
_________
(b4) is reset to “0,” the SBUSY1 output goes to “H” and the SBUSY1
output goes to “L.”
Fig. 25 SBUSY1 Input Operation (internal synchronous clock)
Fig. 26 SBUSY1 Input Operation (external synchronous clock)
(4) Handshake Signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0,” the SSTB1 output goes to “L,” or
________
the SSTB1 output goes to “H.”
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from SOUT1, pulses are output in the pe-
riod of 1 cycle of the transfer clock so as to cause the SSTB1 output
________
to go “H” or the SSTB1 output to go “L.” After that, each pulse is
returned to the initial status in which SSTB1 output goes to “L” or the
________
SSTB1 output goes to “H.”
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0.”
In the automatic transfer serial I/O mode, whether the SSTB1 output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the SBUSY1 output SSTB1
output function selection bit (b4 of address 001A16) of serial I/O1
control register 2.
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
__________
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal
__________
into the SBUSY1 input and an “H” level signal into the SBUSY1 input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
__________
level signal into the SBUSY1 input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immedi-
ately and the transfer clocks from the SCLK1 output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
Fig. 24 SSTB1 Output Operation
SSTB1
SCLK1
SOUT1
Serial transfer
status flag
SBUSY1
SCLK1
SOUT1
SBUSY1
SCLK1
SOUT1
Invalid
(Output high-impedance)
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| M38B52E6XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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| M39012/04-0001 | PANEL MOUNT, CABLE TERMINATED, FEMALE, N CONNECTOR, SOLDER, RECEPTACLE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38B52E6XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B52E6XXXFS | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B52E7XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B52E7XXXFS | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B52E8XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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