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參數(shù)資料
| 型號： | M38B49EDH-XXXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | KJA SERIES III |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 53/78頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | M38B49EDH-XXXXFP |
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53
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Low-order
6-bit data
Data Setup
The PWM output pin also function as port P8
7
. Set port P8
7
to be the
PWM output pin by setting bit 0 of the PWM control register (address
0026
16
) to “1”. The high-order 8 bits of output data are set in the
high-order PWM register PWMH (address 0014
16
) and the low-order
6 bits are set in the low-order PWM register PWML (address 0015
16
).
PWM Operation
The timing of the 14-bit PWM function is shown in
Figure 57.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level signal
is output during each sub-period. There are 64 sub-periods in each
period, and each sub-period t is 256
τ
(= 64 μs) long. The signal’s
“H” has a length equal to N times
τ
, and its minimum resolution = 250
ns.
The last bit of the sub-period becomes the ADD bit which is specified
either “H” or “L”, by the contents of PWML. As shown in Table 10, the
ADD bit is decided either “H” or “L”.
That is, only in the sub-period tm shown in Table 10 in the PWM
cycle period T = 64t, the “H” duration is lengthened during the mini-
mum resolution width
τ
period in comparison with the other period.
For example, if the high-order eight bits of the 14-bit data are “03
16
”
and the low-order six bits are “05
16
”, the length of the “H” level output
in sub-periods t
8
, t
24
, t
32
, t
40
and t
56
is 4
τ,
and its length 3
τ
in all
other sub-periods.
Time at the “H” level of each sub-period almost becomes equal be-
cause the time becomes length set in the high-order 8 bits or be-
comes the value plus
τ
, and this sub-period t (= 64
μ
s, approximate
15.6 kHz) becomes cycle period approximately.
Transfer From Register To Latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 μs), and data written to the
PWMH register is transferred to the PWM latch once in each sub-
period (every 64 μs). When the PWML register is read, the contents
of the latch are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is
completed when bit 7 is “0”.
Table 10 Relationship between low-order 6-bit data and setting
period of ADD bit
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
None
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
LSB
Fig. 57 PWM timing
Sub-periods tm lengthened (m = 0 to 63)
1
5
P
S
S
.
7
5
μ
s
6
4
μ
s
6
4
μ
s
6
4
μ
s
6
4
μ
s
6
4
μ
s
m
=
0
m
=
7
m
=
8
m
=
9
m
=
6
3
1
6
.
0
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
u
l
l
b
b
s
s
e
e
-
p
-
p
w
w
e
e
i
i
i
i
d
d
o
o
t
t
d
d
h
h
m
m
w
w
o
o
h
h
d
d
e
e
u
u
r
r
l
l
e
e
a
a
t
t
“
“
i
i
H
H
o
o
n
n
”
”
p
p
r
r
e
e
u
u
g
g
l
s
l
s
i
i
s
s
e
e
t
t
e
e
w
w
r
r
i
i
d
d
H
L
t
t
:
h
h
0
0
0
0
s
s
1
0
1
1
1
1
6
5
1
0
.
.
1
1
0
7
1
1
u
u
u
:
r
r
s
s
i
i
5
μ
s
μ
:
s
m
:
=
=
8
,
a
2
l
l
4
o
,
t
3
h
2
e
,
r
4
v
0
a
,
l
5
e
6
s
m
u
4
0
9
6
μ
s
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M38B49EEH-XXXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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