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APPENDIX
3886 Group User’s Manual
3.3 Notes on use
3.3.10 Notes on watchdog timer
q Make sure that the watchdog timer does not underflow while waiting Stop release, because the
watchdog timer keeps counting during that term.
q When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a
program.
3.3.11 Notes on RESET pin
(1)
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
Make the length of the wiring which is connected to a capacitor as short as possible.
Be sure to verify the operation of application products on the user side.
s Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.12 Notes on CPU reprogramming mode
(1)
Transfer the CPU reprogramming mode control program to the internal RAM before selecting the
CPU reprogramming mode, and then, execute it on the internal RAM. Additionally, when the subroutine
or stack operation instruction is used in the control program, make sure the control program is not
destroyed by the stack operation.
(2)
Make sure each instruction description (specified address etc.) is correct, because the CPU reprogramming
mode control program is transferred to the internal RAM and executed on the internal RAM.
(3)
In order to avoid generation of a watchdog timer reset, write to the watchdog timer control register
periodically during the CPU reprogramming mode control program (refer to “2.7 Watchdog timer”).
(4)
Notes on flash memory version
The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it
works as a program power source pin (VPP pin), as well.
To improve the noise margin, connect the CNVSS pin to VSS through 1 to 10 k
resistor.
When the CNVSS pin of the mask ROM version is connected to Vss through this resistor, the function
of mask ROM version works well in the same manner as flash memory version.
3.3.13 Notes on using stop mode
sClock restoration
After restoration to the normal mode from the stop mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.