參數(shù)資料
型號(hào)： M38869M8A-XXXGP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 58/110頁(yè)
文件大?。?/td> 1601K
代理商： M38869M8A-XXXGP
58
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK GENERATING CIRCUIT
The 3886 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X
IN
and
X
OUT
(X
CIN
and X
COUT
). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between X
IN
and X
OUT
since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between X
CIN
and X
COUT
.
Immediately after power on, only the X
IN
oscillation circuit starts
oscillating, and X
CIN
and X
COUT
pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock
φ
is the frequency of X
IN
divided by 8. After re-
set, this mode is selected.
(2) High-speed mode
The internal clock
φ
is half the frequency of X
IN
.
(3) Low-speed mode
The internal clock
φ
is half the frequency of X
CIN
.
I
Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both X
IN
and X
CIN
oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately af-
ter power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(X
IN
) > 3f(X
CIN
).
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock X
IN
in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock X
IN
is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock
φ
stops at an
“H” level, and X
IN
and X
CIN
oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF
16
” and timer 1 is set to “01
16
.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either X
IN
or X
CIN
divided by 16 is input to the prescaler 12 as
count source, and the output of the prescaler 12 is connected to
timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before
executing the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock
φ
is not supplied to the
CPU (remains at “H”) until timer 1 underflows. The internal clock
φ
is supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is re-
started by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level, but the oscillator does not stop. The internal clock
φ
re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
Fig. 58 Ceramic resonator circuit
Fig. 59 External clock input circuit
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf
Rd
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C
V
S
C
S
X
C
I
N
X
C
O
U
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X
I
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O
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